This system is based on the SCE-MI protocol, FPGA, BSV language and BSC compiler. It can bring up data interaction channels between the upper software control layer and the underlying algorithm logic implemented on FPGA rapidly. And, It can quickly realize C and Verilog mix Ver Test HyperSilicon Confidential! compilation, rapid mapping with flexible software control mapping running on PC and accelerated logical mapping algorithm running on the FPGA.

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